Compared with other display technologies, LED displays have the advantages of self-illumination, good color recovery performance, high refresh rate, power saving, and easy maintenance. High brightness, splicing and large size are the decisive factors for the rapid growth of LED displays in the past two decades. In the category of large-screen outdoor displays, no other technology can compete with LED display technology.
However, in the past, there was also a lack of LED displays. For example, the distance between the packaged lamp beads is large and the resolution is low, which is not suitable for indoor and close observation. In order to improve the resolution, it is necessary to reduce the spacing between the beads, but the size of the lamp beads is reduced. Although the resolution of the entire screen can be improved, the cost will rise rapidly, and the cost will be too high to affect the small-pitch LED display The wide range of commercial applications. .
In recent years, with the efforts of chip manufacturers and packaging manufacturers, IC circuit manufacturers and screen manufacturers, the cost of single package devices has become lower and lower, LED package devices have become smaller and smaller, and the pixel pitch of display screens has become smaller and smaller. Becoming smaller and smaller. The higher and higher resolution makes the advantages of small-pitch LED displays in indoor large-screen displays more and more obvious.
At present, small-pitch LEDs are mainly used in advertising media, stadiums, stage backgrounds, municipal engineering, etc., and open up markets from time to time in the transportation, broadcasting and military fields. It is estimated that by 2018, the market will be close to 10 billion. It is foreseeable that in the next few years, small-pitch LED displays will expand market share from time to time, squeezing out the market space of DLP rear projection. According to estimates by the Everbright Securities Research Institute, by 2020, the small spacing L
First of all, the demand for LED chips for small-pitch LED displays
The LED chip is the center of the LED display and plays a vital role in the development of small-pitch LEDs. The current achievements and future development of small-pitch LED displays depend on the unremitting efforts of the chip.
On the one hand, the indoor display dot pitch has gradually decreased from P4 in the early days to P1.5, and P1.0 and P0.8 are under development. Correspondingly, the lamp bead size has been reduced from 3535, 2121 to 1010. Some manufacturers have developed 0808 and 0606 sizes, and some manufacturers are developing 0404 sizes.
It is well known that the size of packaging beads is reduced, which inevitably requires a reduction in chip size. At present, the appearance of ordinary blue-green chips for small-pitch displays is about 30 mils2, and local chip factories have mass-produced 25 mils 2 or even 20 mils 2 chips.
On the other hand, the external products of the chip have become smaller and the single-core brightness has dropped, and a series of problems affecting the display quality have become prominent.
The first is the grayscale requirement. Unlike outdoor screens, the difficulty of indoor screen requirements lies not in brightness, but in grayscale. At present, the brightness requirement of indoor large screen is about 1500 cd/m2-2000 cd/m2, the brightness of small-pitch LED display is generally about 600 cd/m2-800 cd/m2, and the best brightness for long-term display is 100 cd. /m2-300cd/m2 or so.
One of the current challenges of small-pitch LED screens is "low light and low gray." In other words, the gray scale is not enough at low brightness. In order to complete "low light and high gray", the current plan on the packaging side is a black bracket. Since the black bracket reflects weakly on the chip, the chip is required to have sufficient brightness.
The second is to show the average problem. Compared with traditional screens, the pitch becomes smaller, which causes problems such as afterglow, first scan darkness, low redness, and low grayscale unevenness. At present, in view of the problems of afterglow, first scan and low gray level, both the package side and the IC control side have tried to effectively alleviate these problems, and the brightness average problem under low gray level has also been corrected point by point. . Technology has eased. However, as one of the root causes of the problem, more efforts are needed on the chip side. In detail, the average brightness is better at a small current, and the parasitic capacitance is better.
The third is the security issue. The current industry standard is that the allowable value of the LED dead rate is one ten thousandth, which is obviously not suitable for small-pitch LED displays. Since the pixel density of the small-pitch screen is relatively large and the observation interval is relatively close, if there is a dead light in 10,000, the effect is unbearable. In the future, the demand for dead-light rate will be controlled at one hundred thousandth or even one millionth to meet the needs of long-term use.
Generally speaking, for the development of small-pitch LEDs, the requirements of the chip part are: size reduction, relative brightness improvement, good brightness divergence at small currents, good parasitic capacitance divergence and high reliability.
Second, the chip end processing plan
1. Size reduction chip size reduction
On the outside, this is a matter of size design. It seems that it can only be dealt with by designing a smaller size according to the requirements. But will the reduction in chip size stop indefinitely? The answer can be negative. There are several reasons for limiting chip size reduction:
(1) Restrictions on packaging processing. In the packaging process, there are two factors that limit the reduction in chip size. One is the limitation of the nozzle. The chip needs to pick up the chip, and the short side of the chip must be larger than the inner diameter of the nozzle. At present, the inner diameter of a cost-effective nozzle is about 80um. The second is the limitation of wire bonding. First of all, the bobbin, that is, the chip electrode must be large enough, otherwise the reliability of the wire bonding cannot be guaranteed. The smallest electrode diameter in the industry is 45um. Secondly, the distance between the electrodes must be large enough, otherwise the two wire bonds will inevitably interfere with each other.
(2) Limitations of chip processing. The processing of the chip also has two limitations. One is the limitation of size planning. In addition to the limitations of the above-mentioned package end, the electrode size and electrode spacing, electrode and MESA spacing, scribe line width, boundary line spacing of different layers, etc. have their limitations, chip current characteristics, SD process capability and photolithography processing capability. . The scope of the detailed restriction has been resolved. Generally, the minimum distance between the P electrode and the edge of the chip will be limited to more than 14 μm.
The second is to limit the cutting ability. The SD cutting + mechanical splicing process has limitations, and the chip size may be too small to be broken. As the diameter of the wafer increases from 2 inches to 4 inches, or to 6 inches in the future, the difficulty of cutting blades increases, and the size of the processed chips will increase. Taking a 4-inch film as an example, if the short side length of the chip is less than 90 microns and the aspect ratio is greater than 1.5:1, the yield loss will increase significantly.
Based on the above reasons, the author boldly predicts that after the chip size is reduced to 17mil2, the chip design and processing can reach the limit. Unless there is a big breakthrough in the chip technology scheme, there is no room for reduction.
2. Increased brightness
Brightness enhancement is a permanent theme for chips. The chip factory optimizes and optimizes internal quantum effects through epitaxial procedures, and enhances external quantum effects through chip structure adjustments.
However, on the one hand, the reduction in chip size inevitably leads to a reduction in the area of the light-emitting area, and the brightness of the chip decreases. On the other hand, the dot pitch of small-pitch displays is reduced, and the brightness requirement of a single chip is reduced. There is a complementary relationship between the two, but there is a bottom line. At present, in order to reduce costs, the chip side mainly subtracts the structure, which usually reduces the brightness. Therefore, how to balance trade-offs is an issue that the industry should pay attention to.
3. Bifurcation under low current
Compare the so-called low current with the current of traditional indoor and outdoor chip tests. As shown in the figure below, the chip I-V curve, the traditional indoor and outdoor chips work in the linear working area, the current is very large. Small-pitch LED chips need to work in a non-linear working area near 0, and the current is too small.
In the non-linear working area, the LED chip is affected by the semiconductor switching threshold, and the difference between the chips is more obvious. In order to analyze the discontinuity of the brightness and wavelength of a large-scale chip, it is easy to see that the dispersion in the non-linear working area is much larger than the dispersion in the linear working area. This is an inherent challenge in current chips.
The method to solve this problem is to optimize the extension direction first to reduce the lower limit of the linear working area; the second is the optimization of chip splitting, which distinguishes different characteristic chips.
4. Parasitic capacitance divergence
Currently, there is no condition on the chip side to directly measure the capacitance characteristics of the chip. The relationship between capacitance characteristics and traditional measurement items is still unclear, and it is waiting for the industry to summarize. The direction of chip side optimization is one-time adjustment, and the other is the improvement of electrical classification, but the cost is high and not recommended.
5. Reliability
Chip packaging reliability can be characterized by various parameters during chip packaging and aging. But in general, the factors that affect the reliability of the chip behind the screen are mainly concentrated on ESD and IR.
ESD refers to the ability to resist static electricity. According to the IC industry, more than 50% of chip failures are related to ESD. In order to improve chip reliability, it is necessary to improve ESD talents. However, under the same epitaxial wafer and the same chip structure, the chip size becomes smaller, which inevitably leads to the weakening of ESD. This is directly related to the current density and chip capacitance characteristics and cannot be resisted.
IR refers to reverse leakage and is usually measured at a fixed reverse voltage. IR reflects the number of defects inside the chip. The larger the IR value, the more obvious the internal defects.
In order to improve ESD and IR performance, more optimizations must be made in the epitaxial structure and chip structure. In the case of chip storage, after strict specifications, ESD and chips with weak IR performance can be effectively removed, thereby improving the reliability of the chips on the chip.
Four, summary
In short, with the advancement of science and the update of the times, the development of the LED display industry has become more and more popular, but the industry effect of the display has finally improved, and the unemployed have been working hard from time to time.
